Master's and Bachelor's Theses
The Systems Group has a variety of projects available, as possible topics for a Masters Thesis, a Semester Projects, or as labs for bachelors or masters students.
Proposals
- protected page Oasis: Accelerating Data Transformations in Data Warehouses [BT/SP/MT] (PDF, 184 KB)
- protected page Understanding and Benchmarking Robotics ML Systems [MT] (PDF, 129 KB)
- protected page Co-Optimizing Performance and Quality for Retrieval-Augmented Generation [MT] (PDF, 1.8 MB)
- protected page Performance Modeling for Vector Databases [MT] (PDF, 1.6 MB)
- protected page Accelerating quantised transformers on FPGAs [SP / MT] (PDF, 193 KB)
- protected page Optimizing Compound AI Systems [MT/Semester Project] (PDF, 112 KB)
- protected page Celeris: Hardware-accelerated Query Engine for Data Analytics [BT/SP/MT] (PDF, 194 KB)
- protected page Implementing Programmable Congestion Control for RoCE-v2 networks on a BlueField-DPU [MT] (PDF, 292 KB)
- protected page Implementing RTT-based Congestion Control in a RoCE-v2 network stack on FPGAs [MT] (PDF, 294 KB)
- protected page Resource Utilization Analysis of Large Video Generation Models Across Datacenter and Consumer GPUs [MT] (PDF, 57 KB)
- protected page FPGA-Accelerated HTTP Server for LLM Inference [MT] (PDF, 82 KB)
- protected page Vector Search and Vector Databases Projects [BT/SP/MT] (PDF, 187 KB)
- protected page A Ternary LLM Accelerator based on FPGA [BT/SP/MT] (PDF, 129 KB)
- protected page Exploring LLMs for Complex Hardware Circuit Design [SP/MT] (PDF, 174 KB)
- protected page Hardware-accelerated Boosted Decision Trees for Computer System Optimization [MT/SP] (PDF, 178 KB)
- protected page Databases and Hardware Acceleration [BT/SP/MT] (PDF, 282 KB)
There are several thesis projects available within the Enzian and Sockeye projects:
- protected page Benchmarking Graph and In-Memory Database Workloads on Enzian (PDF, 135 KB)
- protected page CHERI on the Rocks (PDF, 115 KB)
- protected page CHERIless Cheriette for the Kirsch Project (PDF, 114 KB)
- protected page Finding vulnerabilities and documentation bugs by reasoning about memory accesses on a System-on-Chip: the Applied Micro X-Gene 1 (PDF, 130 KB)
- protected page Integrating ECI and TileLink (PDF, 65 KB)
- protected page Kirsch: Dandelion on Cheriette (PDF, 115 KB)
- protected page Message Tracking for Persistence on Enzian (PDF, 121 KB)
- protected page PCIe for Kirsch and Cheriette (PDF, 113 KB)
- protected page Performance models of far memory systems implemented on Enzian (PDF, 137 KB)
- protected page Restructuring Hyrise's storage manager to support inter-node memory (PDF, 125 KB)
- protected page Rust specification of the Intel 64 and ia32 Memory Management Unit (PDF, 144 KB)
- protected page Rust and Sockeye specification of the RISC-V Memory Management Unit (PDF, 129 KB)
- protected page Sockeye integration forthe Kirsch Project (PDF, 115 KB)
- protected page Sockeye models for the CHERI hardware capability architecture (PDF, 128 KB)
- protected page USB subsystem support for the Kirsch Project (PDF, 113 KB)
- protected page Unmarshaling unit for the Lauberhorn smart NIC (PDF, 137 KB)
- protected page Validation of address translation models against real hardware (PDF, 123 KB)
Contact Timothy Roscoe () if you are interested in any of them.
Contact Michal Friedman () with your CV and transcript of records if you are interested in any of them.