Master's and Bachelor's Theses
The Systems Group has a variety of projects available, as possible topics for a Masters Thesis, a Semester Projects, or as labs for bachelors or masters students.
Proposals
- protected page lock Distributed Graph Neural Network Acceleration on FPGAs for Particle Classification at CERN [MT] (PDF, 255 KB)
- protected page lock Accelerating quantised transformers on FPGAs [SP / MT] (PDF, 193 KB)
- protected page lock Colocation of Inference on FPGA [SP / MT] (PDF, 88 KB)
- protected page lock Efficient Compression of LLM on FPGA [SP / MT] (PDF, 76 KB)
- protected page lock Quantized Vision Transformers on FPGA for Image Feature Extractions [SP / MT] (PDF, 78 KB)
- protected page lock Understanding ML Compilers: A Benchmark on Heterogeneous Hardware [SP / MT] (PDF, 119 KB)
- protected page lock Deploying RoFL at Scale [BT] (PDF, 92 KB)
- protected page lock Cryptographic Audits for Secure Machine Learning [MT] (PDF, 96 KB)
- protected page lock Scheme-Independent FHE Compiler for TensorFlow [MT] (PDF, 75 KB)
- protected page lock Deploying Secure Computation on Heterogeneous Hardware [MT] (PDF, 285 KB)
- protected page lock Differential Private Data and Query Set Generation for Benchmarking (PDF, 85 KB)
- Download lock Low-Latency 64-Channel Stereo Audio Mixing using FPGA [MT/Semester Project] (PDF, 177 KB)
- protected page lock Optimizing Compound AI Systems [MT/Semester Project] (PDF, 112 KB)
- protected page lock Autonomous Driving Benchmarks in Modyn [Semester Project] (PDF, 38 KB)
- protected page lock Extending data selection capabilities in Modyn [Semester Project] (PDF, 34 KB)
- protected page lock LLM Finetuning in Modyn [MT] (PDF, 32 KB)
- protected page lock Multimodality in Mixtera [MT] (PDF, 33 KB)
- protected page lock Parquet File Reader for FPGA-accelerated Cloud Storage Layer (PDF, 194 KB)
There are several thesis projects available within the Enzian and Sockeye projects:
- protected page lock A BMC orchestration layer in Rust over seL4 [BT/MT] (PDF, 98 KB)
- protected page lock High-throughput communication over coherent links [MT] (PDF, 65 KB)
- protected page lock Integrating ECI and TileLink [MT/Practical work] (PDF, 65 KB)
- protected page lock Message Tracking for Persistence on Enzian [MT] (PDF, 121 KB)
- protected page lock Runtime Verification with TeSSLa on Enzian [MT] (PDF, 96 KB)
- protected page lock Rust and Sockeye3 specification of the ARMv8.1-A Memory Management Unit [MT] (PDF, 117 KB)
- protected page lock Rust and Sockeye3 specification of the ARMv8-R Memory Protection Unit [MT] (PDF, 118 KB)
- protected page lock Rust and Sockeye3 specification of the Enzian research computer [MT] (PDF, 118 KB)
- protected page lock Rust and Sockeye3 specification of the Intel 64 and ia32 Memory Management Unit [MT] (PDF, 144 KB)
- protected page lock Rust and Sockeye3 specification of the interconnect of the AMD/Xilinx Ultrascale+ MPSoC [MT] (PDF, 118 KB)
Contact Timothy Roscoe () if you are interested in any of them.