Master's and Bachelor's Theses
The Systems Group has a variety of projects available, as possible topics for a Masters Thesis, a Semester Projects, or as labs for bachelors or masters students.
Proposals
- protected page Optimizing Compound AI Systems [SP/MT] (PDF, 112 KB)
- protected page Hardware-accelerated Boosted Decision Trees for Computer System Optimization [MT/SP] (PDF, 178 KB)
- protected page Databases and Hardware Acceleration [SP/MT] (PDF, 281 KB)
- protected page Accelerating Genetic Algorithms for Routing Problems with Heterogeneous Computer Systems [SP] (PDF, 221 KB)
- protected page Agentic Hardware Design for Data Processing Operators in the Coyote v2-Framework [BT/SP/MT] (PDF, 229 KB)
- protected page Implementation of a FPGA-based Smart Switch [MT] (PDF, 287 KB)
There are several thesis projects available within the NetOS group, related to our main projects Enzian, Kirsch, and Sockeye:
- protected page Achieving readable and maintainable hardware register configuration code: A case study on applying Mackerel2 to the i.MX93 Trusted Resource Domain Controller (PDF, 135 KB)
- protected page CHERIless Cheriette for the Kirsch Project (PDF, 114 KB)
- protected page ECI link simulation (PDF, 132 KB)
- protected page Finding vulnerabilities and documentation bugs by reasoning about memory accesses on a System-on-Chip: the Broadcom BCM2711 and BCM2712 (PDF, 136 KB)
- protected page Finding vulnerabilities and documentation bugs by reasoning about memory accesses on a System-on-Chip: the Nvidia Orin series (PDF, 136 KB)
- protected page Finding vulnerabilities and documentation bugs by reasoning about memory accesses on a System-on-Chip: the Samsung Exynos 9630 (PDF, 136 KB)
- protected page Finding vulnerabilities and documentation bugs by reasoning about memory accesses on a System-on-Chip: the SiFive FU740 RISC-V SoC (PDF, 136 KB)
- protected page Formal Verification of Isolation Properties on the x86 ISA for Userspace Reference Monitors using Memory Protection Keys (PDF, 163 KB)
- protected page Interrupts in Sockeye (PDF, 136 KB)
- protected page Performance models of far memory systems implemented on Enzian (PDF, 137 KB)
- protected page Sockeye models for the CHERI hardware capability architecture (PDF, 128 KB)
- protected page Validation of address translation models against real hardware (PDF, 123 KB)
Contact Timothy Roscoe () if you are interested in any of them.
Contact Michal Friedman () with your CV and transcript of records if you are interested in any of them.